Voltage multipliers increase an input supply voltage in order to provide a higher output voltage required to operate circuit elements in integrated circuits. A charge pump is one type of voltage multiplier typically employed in non-volatile memory systems, such as flash memory systems, to provide voltages required for programming and erasing memory cells in a non-volatile memory. A charge pump typically includes several pump stages which each include a pump capacitor which is charged and discharged during a clock cycle of the charge pump. A stage diode is coupled between the pump capacitor and the stage input voltage to prevent discharging of the pump capacitor prior to the pump capacitor having additional charge placed on it. Thus, a charge pump progressively stores more charge on the capacitor component of each stage, and several such stages being placed together in the charge pump produce an increasing voltage level. In integrated circuits, the diode and the capacitor are typically formed from properly configured transistors.
One or more clock signals typically trigger the charging of the pump capacitors. A typical clock signal has a clock frequency with a time period somewhat less than the discharge time of the pump capacitors. In one such design, two clock signals having opposite phase trigger the charging of alternate stages of a multi-stage charge pump. The opposite phase clock signals in this design permit increasing the amount of charge which can be placed on the pump capacitors.
A conventional pump circuit 20 is illustrated generally in schematic diagram form in FIG. 1A. Pump circuit 20 receives an input supply voltage on a line 22. A first clock signal Ph1 is received on a line 24 and a second clock signal Ph2 having the opposite phase of clock signal Ph1 is received on a line 26. FIG. 1B illustrates typical square wave clock signals Ph1 and Ph2 in timing diagram form. As illustrated in FIG. 1B, clock signals Ph1 and Ph2 have opposite phases and amplitudes corresponding to the amplitude to the input supply voltage on line 22. The input supply voltage on line 22 provides the initial supply of charge for pump circuit 20.
Pump circuit 20 includes N pump stages, as represented by a first pump stage 28 and a second pump stage 30. Clock signal Ph1 is coupled to the first pump stage 28 and clock signal Ph2 is coupled to the second pump stage 30. Similarly, clock signals Ph1 and Ph2 are alternately coupled to the remaining N-2 pump stages of pump circuit 20. Each of the N pump stages comprise a stage transistor figured to function as a diode, such as indicated at 32a for first pump stage 28 and at 32b for second pump stage 30. Each pump stage also includes a pump capacitor, such as indicated at 34a for pump stage 28 and at 34b for pump stage 30. A stray capacitance (C.sub.s), indicated at 36a for pump stage 28 and at 36b for pump stage 30, represents a parasitic capacitance between the substrate of the integrated circuit containing pump circuit 20 and the stage output node for the stage (i.e., the charged node for that pump stage), such as output node VS1 for pump stage 28 and output node VS2 for pump stage 30. Stage transistors 32a and 32b are typically configured to act as diodes by connecting the gate of the transistor to its drain. Pump capacitor 34a is coupled between clock signal Ph1 and the first stage output node VS1 and pump capacitor 34b is coupled between clock signal Ph2 and the second stage output node VS2.
The N pump stages are connected in a serial manner to eventually produce an Nth stage output voltage on a line 40. The Nth stage output voltage is provide to an output transistor 42. Output transistor 42 is configured to act as a diode by connecting its gate to its drain and provides a pump output voltage on a line 44. Output transistor 42 shields the Nth stage output voltage on line 40 from a load (not shown) of the pump circuit 20.
Pump capacitors 34a and 34b are typically implemented in the form of a properly configured transistor, which produces an additional stray capacitance associated with the configured transistor, associated routing, and adjacent devices. This stray capacitance is on the driver side of pump capacitor 34a and 34b. As noted above, there is also a stray capacitance on the pumped node side, which is labeled as 36a and 36b in FIG. 1A. As to the clock driver side stray capacitance (not shown), this capacitance must be charged and discharged with each cycling of the stages of the charge pump, thereby increasing the power required to operate the pump.
The efficiency of pump circuit 20 is defined as the ratio of the output power to input power of the pump circuit, and is represented by the following Equation I: ##EQU1## where, V.sub.supply =Input supply voltage to the pump circuit;
N=number of charge pump stages; PA0 VTN=voltage drop across the diode in a pump stage; PA0 V.sub.dl =voltage drop due to the load current (depends upon N, clock frequency, load current, diode resistance, and pump stage capacitance); PA0 C=pump capacitance per stage; and PA0 C.sup.s =stray capacitance per stage on the pumped node side.
As represented in Equation I, the efficiency of pump circuit 20 can be increased by increasing V.sub.out or by decreasing I.sub.supply for a given number of stages. In one previous design, V.sub.out is increased by employing threshold cancellation techniques and/or by employing transistors configured as diodes with lower threshold voltages for the pump stage diodes. A disadvantage of employing lower threshold voltage transistors is that these transistors require additional manufacturing steps. V.sub.out can also be increased by reducing C.sub.s, which can be accomplished by optimizing the physical implementation of the charge pump.
Another conventional pump circuit is generally illustrated at 50 in FIG. 2A in schematic diagram form. Pump circuit 50 employs a technique of threshold voltage (VT) cancellation to increase the pump output voltage and thereby the efficiency of a charge pump. The VT of a transistor configured to act as a diode corresponds to the VTN voltage drop term of Equation I.
As illustrated in FIG. 2A, pump circuit 50 receives an input supply voltage on a line 52. Pump circuit 50 receives four clock signals (Ph1 on a line 54, Ph2 on a line 56, Ph1a on a line 58, and Ph2a on a line 60) to control the operation of pump circuit 50. Clock signals Ph1, Ph1a, Ph2 and Ph2a are illustrated in timing diagram form in FIG. 2B. As illustrated in FIG. 2B, clock signals Ph1 and Ph2 are typically square waves having opposite phase, while clock signals Ph1a and Ph2a are square waves that have smaller duty cycles than clock signals of Ph1 and Ph2, such that clock Ph1a and Ph2a have a shorter time at active high values than the time clock signals Ph1 and Ph2 are at active high values.
A first pump stage 62 comprises a stage transistor 66a and a second pump stage 64 comprises a stage transistor 66b where transistors 66a-b are configured to act as diodes. Pump stage 62 includes a pump capacitor 68a coupled between clock signal Ph1 and an output node VS1 of first pump stage 62. Similarly, pump stage 64 includes a pump capacitor 68b coupled between clock signal Ph2 and an output node VS2 of pump stage 64. A capacitance indicated at 70a and 70b represents the stray capacitance (C.sub.s) on the charged node side of pump stages 62 and 64 respectively. In addition, a capacitance labeled 72a and 72b represents the stray capacitance (C.sub.c) of pump capacitors 68a and 68b respectively on the clock side of the pump circuit which arises when pump capacitors 68a-b are implemented in the form of properly configured transistors or other such fabricated capacitors.
Pump stages 62 and 64 also include VT canceler circuits 74a and 74b respectively. VT canceler circuit 74a includes a canceler capacitor 76a coupled between the Ph2a clock signal on line 60 and a VG1 node at the gate of stage transistor 66a. VT canceler circuit 74a also includes a switching N-channel transistor 78a having its source coupled to the input supply voltage on line 52, its drain coupled to node VG1, and its gate coupled to the stage output node VS1, such that when switching transistor 78a is switched on stage transistor 66a becomes configured to act as a diode connected between the input supply voltage on line 52 and the stage output voltage on node VS1. Similarly, VT canceler 74b includes a canceler capacitor 76b coupled between clock signal Ph1a on line 58 and a node VG2 at the gate of stage transistor 66b. VT canceler 74b also includes a switching N-channel transistor 78b having its source coupled to the input of pump stage 64 at node VS1, its drain coupled to node VG2, and its gate coupled to the stage output node VS2.
An output transistor 80 is configured as a diode by coupling its gate to its drain, and provides a pump output voltage on an output line 82. Output transistor 80 is coupled between stage output node VS2 and the pump output voltage on output line 82. Output transistor 80 shields the final pumped voltage at node VS2 from the load or output capacitance connected to output line 82.
The VT cancellation operation of pump circuit 50 is better understood by referring to the clock timing diagram of FIG. 2B along with the schematic diagram FIG. 2A. At time T1, clock signal Ph1 goes active high to cause pump capacitor 68a to be charged. As a result, node VS1 is pumped by an amount of voltage which is based on the ratio of the capacitances of capacitors 68a and 70a. The increased voltage on VS1 is fed to the gate of switching transistor 78a which turns on transistor 78a, to thereby effectively connect the input supply voltage on line 52 to node VG1. Prior to time T2, clock signal Ph1 goes inactive low, and at time T2, clock signal Ph2a goes active high to cause canceler capacitor 76a to charge which pumps the voltage at node VG1. Consequently, the voltage at node VG1 is pumped above the input supply voltage level on line 52.
The VG1 node voltage at the gate of stage transistor 66a being above the level of the input supply voltage at the drain of stage transistor 66a turns on stage transistor 66a to permit charging of node VS1 to the input supply voltage level on line 52. Therefore, VT canceler circuit 74a compensates for the VT drop across transistor 66a. Without VT canceler circuit 74a, the threshold voltage drop would cause the voltage at node VS1 to be equal to the input supply voltage minus VT (where VT is the threshold voltage drop of stage transistor 66a). With VT canceler circuit 74a, the voltage available at node VS1 is increased substantially to the input supply voltage, which can then be used as a base line voltage for the next pump stage 64.
At time T3, the voltage level of node VS1 is at the input supply voltage level on line 52. On the rising edge of clock signal Ph1, starting at time T3, node VS1 is pumped up from the input supply voltage level. Clock signals Ph2 and Ph1a are then employed to control pump circuit 50 to increase the voltage at node VS2 with second pump stage 64. Second pump stage 64 operates similar to first pump stage 62 as described above, except that, instead of pre-charging VS2 to a level corresponding to the input voltage supply, node VG2 is pre-charged to a level equal to that of the voltage at node VS1. Clock signal Ph2 is employed to charge capacitor 68b to turn on switching transistor 78b to thereby connect node VS1 to VG2. Clock signal Ph1a is then employed to charge capacitor 76b to thereby pump node VG2. Pumping node VG2 turns on stage transistor 66b which charges node VS2 to a level corresponding to node VS1. Without VT canceler circuit 76b, node VS2 would be charged only to the level of VS1 minus VT (where VT is the threshold voltage drop of stage transistor 66b).
Although the implementation of VT canceler circuits 74a and 74b increases the efficiency of a charge pump having pump circuit 50 by increasing V.sub.out by employing the next pump stage to cancel the VT of the previous pump stage, there is still a need in the art of integrated circuit design, and in the particular, design of memory integrated circuits, such as non-volatile memory systems using programming voltages for programming and erasing memory cells, for charge pump circuits which are more efficient by increasing V.sub.out without increasing the input supply power. For reasons stated above and for other reasons presented in greater detail in the Description of the Preferred Embodiments section of the present specification, any significant increase in efficiency of charge pumps is strongly desired when the charge pumps are in integrated circuits operating with low supply voltages and small load currents and with reduced power consumption as a major design concern, such as charge pumps in non-volatile memory integrated circuits.